UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 637

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1. If the CBnRX register is read with the CBnSCE bit set to 1, the
Caution Be sure to clear bits 3 and 2 to “0”.
CBnSCE
This bit enables or disables the communication start trigger in reception mode.
• In master mode
• In slave mode
[Usage of CBnSCE bit]
• In single reception mode
• In continuous reception mode
(a) In single transmission or transmission/reception mode, or continuous
(b) In single reception mode:
(c) In continuous reception mode
Set the CBnSCE bit to 1.
<1>When reception of the last data is completed by INTCBnR interrupt
<2> After confirming that the CBnSTR.CBnTSF bit is 0, clear the CBnPWR and
<1> Clear the CBnSCE bit to 0 in the INTCBnR interrupt servicing for the receive
<2>Read the CBnRX register.
<3>Read the last reception data by reading the CBnRX register after
<4> After confirming that the CBnSTR.CBnTSF bit is 0, clear the CBnPWR and
0
1
transmission or continuous transmission/reception mode:
The setting of the CBnSCE bit has no effect on communication.
Clear the CBnSCE bit to 0 before reading the last receive data to disable the
start of reception because reception is started by reading the receive data
(CBnRX register)
Clear the CBnSCE bit to 0 one communication clock cycle before reception of
the last data is completed to disable the start of reception after the last data is
received
servicing, clear the CBnSCE bit to 0 before reading the CBnRX register.
CBnRXE bits to 0 to disable reception.
To receive data again, set the CBnSCE bit to 1 to start the next reception
by dummy-reading the CBnRX register.
data immediately before the last one.
acknowledging the CBnTIR interrupt.
CBnRXE bits to 0 to disable reception.
To receive data again, set the CBnSCE bit to 1 to wait for the next reception
by dummy-reading the CBnRX register.
2. If the CBnSCE bit is not cleared to 0, one communication clock
Communication start trigger invalid
Communication start trigger valid
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
next communication is started.
cycle before reception of the last data is completed, the next
communication is automatically started.
Note 2
.
Note 1
Specification of start transfer disable/enable
.
User’s Manual U18953EJ5V0UD
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