UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 782

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

780
(5) Procedure for temporarily stopping DMA transfer (clearing Enn bit)
(6) Memory boundary
(7) Transferring misaligned data
(b) Repeatedly setting the INITn bit until transfer is forcibly terminated correctly
Stop and resume the DMA transfer under execution using the following procedure.
<1> Suppress a transfer request from the DMA request source (stop operation of the on-chip peripheral I/O).
<2> Check the DMA transfer request is not held pending, by using the DFn bit (check if the DFn bit = 0).
<3> Check the TCn bit to confirm that DMA transfer is not complete (confirm that the TCn bit is 0). If the TCn
<4> If it has been confirmed that no DMA transfer request is held pending, clear the Enn bit to 0 (this
<5> Set the Enn bit to 1 to resume DMA transfer.
<6> Resume the operation of the DMA request source that has been stopped (start operation of the on-chip
The operation is not guaranteed if the address of the transfer source or destination exceeds the area of the
DMA source or destination (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer.
(For details about the addresses of each area, see Figure 3-2.)
DMA transfer of misaligned 16-bit data is not supported.
If an odd address is specified as the transfer source or destination, the least significant bit of the address is
forcibly handled as 0.
<1> Before starting DMA, copy the initial number of transfers of the channel to be forcibly terminated to a
<2> Suppress a request from the DMA request source for the channel to be forcibly terminated (stop
<3> Check that the DMA transfer request for the channel to be forcibly terminated is not held pending, by
<4> When it has been confirmed that the DMA request for the channel to be forcibly terminated is not held
<5> Again, clear the Enn bit for the channel to be forcibly terminated to 0.
<6> Set the INITn bit of the channel to be forcibly terminated to 1.
<7> Read the value of the DBCn register corresponding to the channel to be forcibly terminated, and
Remarks 1. When the value of the DBCn register is read in <7>, the initial number of transfers is read if
If a request is held pending, wait until execution of the pending DMA transfer request is completed.
bit is 1, execute the DMA transfer completion processing.
operation suspends DMA transfer).
peripheral I/O).
general-purpose register.
operation of the on-chip peripheral I/O).
using the DTFRn.DFn bit. If a DMA transfer request is held pending, wait until execution of the
pending DMA transfer request is completed.
pending, clear the Enn bit to 0.
If the internal RAM is the transfer source or destination of the channel to be forcibly terminated,
execute this operation again.
compare it with the value copied in <1>. If the two values do not match, repeat operations <6> and
<7>.
2. Note that method (b) may take a long time if the application frequently uses DMA transfer for
forced termination has been correctly completed. If not, the remaining number of transfers
is read.
a channel other than the DMA channel to be forcibly terminated.
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
User’s Manual U18953EJ5V0UD