UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 745

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19.16.1 Master operation in single master system
Note Release the I
Remarks 1. For the transmission and reception formats, conform to the specifications of the product involved
product involved in the communication.
For example, when the EEPROM
pin and output clock pulses from that output pin until the SDA0n pin is constantly high level.
2. n = 0 to 2, m = 0, 1
in the communication.
2
C0n bus (SCL0n, SDA0n pins = high level) in compliance with the specifications of the
No
No
Figure 19-18. Master Operation in Single Master System
ACKEn = WTIMn = SPIEn = 1
Set STCENn, IICRSVn = 0
Transfer completed?
Initialize I
interrupt occurred?
interrupt occurred?
interrupt occurred?
OCKSm ← XXH
IICCLn ← XXH
SVAn ← XXH
IICCn ← XXH
STCENn = 1?
IICXn ← 0XH
IICFn ← 0XH
ACKDn = 1?
ACKDn = 1?
Restarted?
TRCn = 1?
Write IICn
Write IICn
IICEn = 1
Set ports
SPTn = 1
STTn = 1
INTIICn
INTIICn
INTIICn
START
2
C bus
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Note
TM
outputs a low level to the SDA0n pin, set the SCL0n pin as an output
User’s Manual U18953EJ5V0UD
Waiting for stop condition detection
Yes
No
No
No
No
No
No
Communication start preparation
(stop condition generation)
Refer to Table 4-15 Settings When Pins Are Used for Alternate Functions
to set the I
Transfer clock selection
Local address setting
Start condition setting
Communication start preparation
(start condition generation)
Communication start
(address, transfer direction specification)
Waiting for ACK detection
Transmission start
Waiting for data transmission
CHAPTER 19 I
SPTn = 1
2
END
C mode before this function is used.
2
C BUS
Transfer completed?
WTIMn = WRELn = 1
interrupt occurred?
interrupt occurred?
WRELn = 1
ACKEn = 1
WTIMn = 0
ACKEn = 0
Read IICn
INTIICn
INTIICn
Yes
Yes
Yes
No
No
No
Reception start
Waiting for
data reception
Waiting for ACK detection
743

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