UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 538

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

536
(8) Reading ADA0CRn register
(9) Standby mode
(10) High-speed conversion mode
(11) A/D conversion time
(12) Variation of A/D conversion results
When the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written, the contents of the
ADA0CRn register may be undefined. Read the conversion result after completion of conversion and before
writing to the ADA0M0 to ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register. Also, when an external/timer
trigger is acknowledged, the contents of the ADA0CRn register may be undefined. Read the conversion result
after completion of conversion and before the next external/timer trigger is acknowledged.
conversion result may not be read at a timing different from the above.
Because the A/D converter stops operating in the STOP mode, power consumption can be reduced, but the
conversion results will be invalid. Operations are resumed after the STOP mode is released, but the A/D
conversion results after the STOP mode is released are invalid. When using the A/D converter after the STOP
mode is released, before setting the STOP mode or releasing the STOP mode, clear the ADA0M0.ADA0CE bit
to 0 then set the ADA0CE bit to 1 after releasing the STOP mode.
In the IDLE1, IDLE2, or subclock operation mode, operation continues. In the IDLE1 and IDLE2 modes, since
the analog input voltage value cannot be retained, the A/D conversion results after the IDLE1 and IDLE2
modes are released are invalid. The results of conversions before the IDLE1 and IDLE2 modes were set are
valid. To lower the power consumption, therefore, clear the ADA0M0.ADA0CE bit to 0.
In the high-speed conversion mode, rewriting the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT
registers and inputting a trigger during the stabilization time are prohibited.
A/D conversion time is the total time of stabilization time, conversion time, wait time, and trigger response
time (for details of these times, refer to Table 14-2 Conversion Time Selection in Normal Conversion
Mode (ADA0HS1 Bit = 0) and Table 14-3 Conversion Time Selection in High-Speed Conversion Mode
(ADA0HS1 Bit = 1)).
During A/D conversion in the normal conversion mode, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and
ADA0PFT registers are written or a trigger is input, reconversion is carried out. However, if the stabilization
time end timing conflicts with writing to these registers, or if the stabilization time end timing conflicts with the
trigger input, the stabilization time of 64 clocks is reinserted.
If a conflict occurs again with the reinserted stabilization time end timing, the stabilization time is reinserted.
Therefore do not set the trigger input interval and control register write interval to 64 clocks or lower.
The results of the A/D conversion may vary depending on the fluctuation of the supply voltage, or may be
affected by noise. To reduce the variation, take countermeasures in the program such as averaging the A/D
conversion results.
CHAPTER 14 A/D CONVERTER
User’s Manual U18953EJ5V0UD
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