UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 92

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

90
(3) System status register (SYS)
Status flags that indicate the operation status of the overall system are allocated to this register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The PRERR flag operates under the following conditions.
(a) Set condition (PRERR flag = 1)
(b) Clear condition (PRERR flag = 0)
(i) When data is written to a special register without writing anything to the PRCMD register (when <4> is
(ii) When data is written to an on-chip peripheral I/O register other than a special register (including
Remark
(i) When 0 is written to the PRERR flag
(ii) When the system is reset
Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,
executed without executing <3> in 3.4.7 (1) Setting data to special registers)
execution of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.7 (1)
Setting data to special registers is not the setting of a special register)
After reset:
SYS
2. If data is written to the PRCMD register, which is not a special register, immediately
Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction) or the
internal RAM is accessed between an operation to write the PRCMD register and an operation
to write a special register, the PRERR flag is not set, and the set data can be written to the
special register.
PRERR
immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0
(the write access takes precedence).
after a write access to the PRCMD register, the PRERR bit is set to 1.
00H
0
1
0
Protection error did not occur.
Protection error occurred.
R/W
0
Address:
CHAPTER 3 CPU FUNCTION
User’s Manual U18953EJ5V0UD
0
FFFFF802H
Detects protection error
0
0
0
0
PRERR
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