UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 834

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.3 HALT Mode
23.3.1 Setting and operation status
to the other on-chip peripheral functions continues.
set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating.
normal operation mode.
23.3.2 Releasing HALT mode
unmasked external interrupt request signal (INTP0 to INTP7 pin input), unmasked internal interrupt request signal
from a peripheral function operable in the HALT mode, or reset signal (reset by RESET pin input, WDT2RES signal,
low-voltage detector (LVI), or clock monitor (CLM)).
832
Reset
Non-maskable
interrupt request
signal (excluding
multiple interrupts)
Maskable interrupt
request signal
Release Source
The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode.
In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply
As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was
Table 23-3 shows the operating status in the HALT mode.
The average current consumption of the system can be reduced by using the HALT mode in combination with the
Cautions 1. Insert five or more NOP instructions after the HALT instruction.
The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
After the HALT mode has been released, the normal operation mode is restored.
(1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request. If the HALT mode is set in an interrupt
servicing routine, however, an interrupt request that is issued later is serviced as follows.
2. If the HALT instruction is executed while an unmasked interrupt request signal is being held
pending, the status shifts to HALT mode, but the HALT mode is then released immediately by
the pending interrupt request.
Acknowledgment
Disabled (DI)
Enabled (EI)
Disabled (DI)
Enabled (EI)
Disabled (DI)
Enabled (EI)
Interrupt
Status
Table 23-2. Releasing HALT Mode and Operation After Release
• An interrupt request with a
• An interrupt request with a
priority higher than that of
the release source is being
serviced.
priority lower than that of
the release source is being
serviced.
Status After Release
CHAPTER 23 STANDBY FUNCTION
User’s Manual U18953EJ5V0UD
−
−
−
Normal reset operation
The interrupt request is acknowledged when the HALT
mode is released.
The HALT mode is released but the interrupt request that
is the release source is not acknowledged. The interrupt
request itself is retained. The processing that was being
executed before shifting to the HALT mode is executed.
The HALT mode is released but the interrupt request that
is the release source is not acknowledged. The interrupt
request itself is retained. The interrupt that was being
serviced before shifting to the HALT mode is serviced.
The interrupt request is acknowledged when the HALT
mode is released.
Operation After Release