UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 356

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

with the count clock, and the counter starts incrementing. At this time, the output of the TOQ00 pin is inverted and the
set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
0000H, the output of the TOQ00 pin is inverted, and a compare match interrupt request signal (INTTQ0CC0) is
generated.
354
TQ0CTL1
When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
When the value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to
The interval can be calculated by using the following expression:
An example of the register settings when the interval timer mode is used is shown in the figure below.
Interval = (Set value of TQ0CCR0 register + 1) × Count clock cycle
(a) TMQ0 control register 0 (TQ0CTL0)
(b) TMQ0 control register 1 (TQ0CTL1)
TQ0CTL0
Note The TQ0EEE bit can only be set to 1 when the timer output (TOQ0k) is used. Note that when
0
setting the TQ0EEE bit to 1, the TQ0CCR0 and TQ0CCRk registers must be set to the same
value (that is, the same value as the value already specified for these registers). (For details,
see 8.4.1 (2) (d) Operation of TQ0CCR1 to TQ0CCR1 registers.) (k = 1 to 3.)
TQ0CE
0/1
TQ0EST
0
Figure 8-8. Register Settings in Interval Timer Mode (1/3)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0
TQ0EEE
0/1
Note
0
0
User’s Manual U18953EJ5V0UD
0
0
0
TQ0MD2 TQ0MD1 TQ0MD0
0
TQ0CKS2 TQ0CKS1 TQ0CKS0
0/1
0
0/1
0
0/1
0, 0, 0:
Interval timer mode
0: Increment based on the
1: Increment based on the
TQ0CKS0 to TQ0CKS2 bits.
count clock selected by the
input of an external event
count signal.
These bits select
the count clock.
0: Stop counting
1: Enable counting