UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 787

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Maskable
Note
Type
μ
Default
Priority
PD70F3792, 70F3793 only
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
INTTP3OV
(/INTUA5R)
INTTP3CC0
INTTP3CC1
(/INTUA5T)
INTTP4OV
INTTP4CC0
INTTP4CC1
INTTP5OV
INTTP5CC0
INTTP5CC1
INTTM0EQ0 TMM0 compare match
INTCB0R/
INTIIC1
INTCB0T
INTCB1R
INTCB1T
INTCB2R
INTCB2T
INTCB3R
INTCB3T
INTUA0R/
INTCB4R
INTUA0T/
INTCB4T
INTUA1R/
INTIIC2
INTUA1T
INTUA2R/
INTIIC0
CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
Name
Note
Note
TMP3 overflow/
INTUA5 reception completion/
UARTA5 reception error
TMP3 capture 0/compare 0 match
TMP3 capture 1/compare 1 match/
INTUA5 successive transmission enable
TMP4 overflow
TMP4 capture 0/compare 0 match
TMP4 capture 1/compare 1 match
TMP5 overflow
TMP5 capture 0/compare 0 match
TMP5 capture 1/compare 1 match
CSIB0 reception completion/
CSIB0 reception error/
IIC1 transfer completion
CSIB0 successive transmission write
enable
CSIB1 reception completion/
CSIB1 reception error
CSIB1 successive transmission write
enable
CSIB2 reception completion/
CSIB2 reception error
CSIB2 successive transmission write
enable
CSIB3 reception completion/
CSIB3 reception error
CSIB3 successive transmission write
enable
UARTA0 reception completion/
UARTA0 reception error/
CSIB4 reception completion/
CSIB4 reception error
UARTA0 successive transmission
enable/CSIB4 successive transmission
write enable
UARTA1 reception completion/
UARTA1 reception error/
IIC2 transfer completion
UARTA1 successive transmission enable UARTA1
UARTA2 reception completion/
UARTA2 reception error/
IIC0 transfer completion
Table 21-1. Interrupt Source List (2/3)
User’s Manual U18953EJ5V0UD
Trigger
TMP4
TMP5
TMP3/
UARTA5
TMP3
TMP3/
UARTA5
TMP4
TMP4
TMP5
TMP5
TMM0
CSIB0/
IIC1
CSIB0
CSIB1
CSIB1
CSIB2
CSIB2
CSIB3
CSIB3
UARTA0/
CSIB4
UARTA0/
CSIB4
UARTA1/
IIC2
UARTA2/
IIC0
Generating
Unit
01F0H
0200H
0210H
0220H
0230H
0240H
0250H
0260H
0270H
0280H
0290H
02A0H
02B0H
02C0H
02D0H
02E0H
02F0H
0300H
0310H
0320H
0330H
0340H
0350H
Exception
Code
000001F0H
00000200H
00000210H
00000220H
00000230H
00000240H
00000250H
00000260H
00000270H
00000280H
00000290H
000002A0H
000002B0H
000002C0H
000002D0H
000002E0H
000002F0H
00000300H
00000310H
00000320H
00000330H
00000340H
00000350H
Address
Handler
TP3OVIC/
UA5RIC
TP3/CCIC0
TP3CCIC1/
UA5TIC
TP4OVIC
TP4CCIC0
TP4CCIC1
TP5OVIC
TP5CCIC0
TP5CCIC1
TM0EQIC0
CB0RIC/
IICIC1
CB0TIC
CB1RIC
CB1TIC
CB2RIC
CB2TIC
CB3RIC
CB3TIC
UA0RIC/
CB4RIC
UA0TIC/
CB4TIC
UA1RIC/
IICIC2
UA1TIC
UA2RIC/
IICIC0
Interrupt
Register
Control
785