UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 764

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

762
(3) DMA transfer count registers 0 to 3 (DBC0 to DBC3)
Cautions 1. Set the DBCn register during one of the following periods in which DMA transfer is
The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3).
These registers hold the remaining transfer count during DMA transfer.
These registers are decremented by 1 per transfer regardless of the transfer data unit (8/16 bits), and the
transfer is terminated if a borrow occurs.
The number of transfers specified first is held when DMA transfer is complete.
These registers can be read or written in 16-bit units.
2. Following a reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before
(n = 0 to 3)
DBCn
disabled (DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
starting DMA transfer. If these registers are not set, DMA transfers are not guaranteed.
After reset:
DMA transfer
BC15
15
BC15 to
FFFFH
0000H
0001H
BC0
Undefined
:
BC14
14
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
BC13
13
1st byte transfer or remaining byte transfer count
2nd byte transfer or remaining byte transfer count
:
65,536 (2
BC12
12
R/W
BC11
User’s Manual U18953EJ5V0UD
16
11
)th byte transfer or remaining byte transfer count
BC10
Address:
10
Byte transfer count setting or remaining
byte transfer count during DMA transfer
BC9
9
DBC0 FFFFF0C0H, DBC1 FFFFF0C2H,
DBC2 FFFFF0C4H, DBC3 FFFFF0C6H
BC8
8
BC7
7
BC6
6
BC5
5
BC4
4
BC3
3
BC2
2
BC1
1
BC0
0