UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 588

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.8 Cautions
586
(1) When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation
(2) The RXDA1 and KR7 pins must not be used at the same time. When using the RXDA1 pin, do not use the
(3) In UARTAn, the interrupt caused by a communication error does not occur. When transferring transmit data
(4) RXDA0 and INTP7 use the same pin. To use the pin for the RXDA0 function, disable edge detection for INTP7
(5) Start up UARTAn in the following sequence.
(6) Stop UARTAn in the following sequence.
(7) In transmit mode (UAnCTL0.UAnPWR bit = 1 and UAnCTL0.UAnTXE bit = 1), do not overwrite the same value
(8) In continuous transmission, the period from the stop bit to the next start bit is 2 base clock cycles longer than
(9) UARTA cannot identify the start bit if low level signals are continuously input to the RXDAn pin.
and receive data using DMA transfer, error processing cannot be performed even if errors (parity, overrun,
framing) occur during transfer. Either read the UAnSTR register after DMA transfer has been completed to
make sure that there are no errors, or read the UAnSTR register during communication to check for errors.
(INTF3.INTF31 bit = 0, INTR3.INTR31 bit = 0).
<1> Set the UAnCTL0.UAnPWR bit to 1.
<2> Set the ports.
<3> Set the UAnCTL0.UAnTXE bit to 1 and the UAnCTL0.UAnRXE bit to 1.
to the UAnTX register by software because transmission starts by writing to this register. To transmit the same
value continuously, overwrite the same value.
usual. However, the reception side initializes the timing by detecting the start bit, so the reception result is not
affected.
stops with each register retaining the value it had immediately before the clock supply was stopped. The
TXDAn pin output also holds and outputs the value it had immediately before the clock supply was stopped.
However, the operation is not guaranteed after the clock supply is resumed. Therefore, after the clock supply
is resumed, the circuits should be initialized by setting the UAnCTL0.UAnPWR, UAnCTL0.UAnRXEn, and
UAnCTL0.UAnTXEn bits to 0, 0, 0.
KR7 pin. When using the KR7 pin, do not use the RXDA1 pin. (It is recommended to set the PFC91 bit to 1
and clear PFCE91 bit to 0.)
<1> Set the UAnCTL0.UAnTXE bit to 0 and the UAnCTL0.UAnRXE bit to 0.
<2> Set the ports and set the UAnCTL0.UAnPWR bit to 0 (it is not a problem if the port settings are not
changed).
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
User’s Manual U18953EJ5V0UD