UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 93

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.4.8
registers after setting the above registers.
Be sure to set the following registers first when using the V850ES/JG3-L.
• System wait control register (VSWC)
• On-chip debug mode register (OCDM)
• Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-related
(a) System wait control register (VSWC)
(b) On-chip debug mode register (OCDM)
(c) Watchdog timer mode register 2 (WDTM2)
Registers to be set first
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.
Three clock cycles are required to access an on-chip peripheral I/O register (without a wait cycle). The
V850ES/JG3-L requires wait cycles according to the operating frequency. Set the following value to the
VSWC register in accordance with the frequency used.
This register can be read or written in 8-bit units.
Reset sets this register to 77H (number of waits: 14).
For details, see CHAPTER 31 ON-CHIP DEBUG FUNCTION.
The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.
Watchdog timer 2 automatically starts in the reset mode after reset is released. To specify the operation of
watchdog timer 2, write to the WDTM2 register after reset is released.
For details, see CHAPTER 12 WATCHDOG TIMER 2.
VSWC
After reset:
Operating Frequency (f
16.6 MHz ≤ f
77H
32 kHz ≤ f
7
R/W
CLK
6
CLK
< 16.6 MHz
≤ 20 MHz
CHAPTER 3 CPU FUNCTION
Address:
User’s Manual U18953EJ5V0UD
CLK
5
)
FFFFF06EH
Set Value of VSWC
4
00H
01H
3
2
Number of Waits
0 (no waits)
1
1
0
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