UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 38

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(10) Real-time counter (for watch) (
(11) Watchdog timer 2
(12) Serial interface
(13) A/D converter
(14) D/A converter
(15) DMA controller
(16) Key interrupt function
(17) Real-time output function
(18) CRC function
The real-time counter counts the reference time (one second) for watch counting based on the subclock
(32.768 kHz) or main clock. This can simultaneously be used as the interval timer based on the main clock.
Hardware counters dedicated to year, month, day of week, day, hour, minute, and second are provided, and
can count up to 99 years.
A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.
The internal oscillator clock, the main clock, or the subclock can be selected as the source clock.
Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal
(WDT2RES) after an overflow occurs.
The V850ES/JG3-L includes three kinds of serial interfaces: asynchronous serial interface A (UARTA),
asynchronous serial interface C (UARTC), 3-wire variable-length serial interface B (CSIB), and an I
interface (I
In the case of UARTA, data is transferred via the TXDA0 to TXDA5 pins and RXDA0 to RXDA5 pins.
In the case of UARTC, data is transferred via the TXDC0 pin and RXDC0 pin.
In the case of CSIB, data is transferred via the SOB0 to SOB4 pins, SIB0 to SIB4 pins, and SCKB0 to
SCKB4 pins.
In the case of I
This 10-bit A/D converter includes 12 analog input pins. Conversion is performed using the successive
approximation method.
A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip.
A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8
channels).
The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer
compare register match signal.
A CRC operation circuit that generates a 16-bit CRC (Cyclic Redundancy Check) code upon the setting of 8-
bit data is provided on-chip.
2
C).
2
C, data is transferred via the SDA00 to SDA02 and SCL00 to SCL02 pins.
μ
PD70F3792, 70F3793 only)
CHAPTER 1 INTRODUCTION
User’s Manual U18953EJ5V0UD
2
C bus