UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 648

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

646
SIBn pin capture
INTCBnR signal
CBnTSF bit
SCKBn pin
Figure 18-10. Single Transfer Mode Operation Timing (Master Mode, Transmission/Reception Mode)
SOBn pin
SIBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E1H to the CBnCTL0 register, and select the transmission/reception mode and MSB first at the
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and
(5) When transmission/reception is started, output the serial clock to the SCKBn pin, output the transmit
(6) When transmission/reception of data of the transfer data length set by the CBnCTL2 register is
(7) Read the CBnRX register.
(8) To continue transmission/reception, repeat the above steps from (4).
(9) Read the CBnRX register.
(10) To
Remark
timing
f
same time as enabling the operation of the communication clock (f
transmission/reception is started.
data to the SOBn pin in synchronization with the serial clock, and capture the receive data of the SIBn
pin.
completed, stop the serial clock output, transmit data output, and data capturing, generate the
reception complete interrupt request signal (INTCBnR) at the last edge of the serial clock cycle, and
clear the CBnTSF bit to 0.
CBnCTL0.CBnRXE bits to 0.
XX
/2, and master mode.
(1)
(2)
(3)
end
n = 0 to 4
(4)
(5)
transmission/reception,
Bit 7
Bit 7
Bit 6
Bit 6
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 5
Bit 5
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
User’s Manual U18953EJ5V0UD
clear
Bit 1
Bit 1
(6)
(7)
the
Bit 0
Bit 0
(8)
CBnCTL0.CBnPWR,
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
CCLK
Bit 4
Bit 4
).
Bit 3 Bit 2
Bit 3 Bit 2
CBnCTL0.CBnTXE,
Bit 1
Bit 1
Bit 0
Bit 0
(9)
(10)
CCLK
and
) =