UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 493
UPD70F3738GF-GAS-AX
Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet
1.UPD70F3737GF-GAS-AX.pdf
(1071 pages)
Specifications of UPD70F3738GF-GAS-AX
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
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Company:
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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12.3 Registers
(1) Watchdog timer mode register 2 (WDTM2)
Note
Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 11-2 Loop Detection Time Interval
The WDTM2 register sets the overflow time and operation clock of watchdog timer 2.
This register can be read or written in 8-bit units. This register can be read any number of times, but it can be
written only once following reset release.
Reset sets this register to 67H.
Caution Accessing the WDTM2 register is prohibited in the following statuses. Moreover, if the
When the option byte function is used, if the WDTMD1 bit is set (to 1), the WMD21 and WDM20 bits
are fixed to 1 (which specifies the reset mode), and the WDCS24 and WDCS23 bits are fixed to 0
(which specifies the internal oscillation clock (f
29 OPTION BYTE.
2. If the WDTM2 register is rewritten twice after a reset, an overflow signal is forcibly
3. To intentionally generate an overflow signal, write data to the WDTM2 register twice, or
4. To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop the
WDTM2
of Watchdog Timer 2.
generated and the counter is reset.
write a value other than “ACH” to the WDTE register once.
However, when watchdog timer 2 is set to “stop operation”, an overflow signal is not
generated even if data is written to the WDTM2 register twice, or a value other than “ACH”
is written to the WDTE register once.
internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP bit cannot be
set to 1, set the WDCS23 bit to 1 (2
IDLE1, IDLE2, sub-IDLE, and subclock operation modes).
system is in the wait status, the only way to cancel the wait status is to execute a reset. For
details, see 3.4.9 (1) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and main clock oscillation is stopped
• When the CPU operates on the internal oscillator clock
After reset: 67H
WDM21
0
0
1
0
WDM21
WDM20
R/W
0
1
-
CHAPTER 12 WATCHDOG TIMER 2
Note
Address: FFFFF6D0H
Stops operation
Non-maskable interrupt request mode
(generation of INTWDT2 signal)
Reset mode (generation of WDT2RES signal)
WDM20
User’s Manual U18953EJ5V0UD
Note
Selection of operation mode of watchdog timer 2
WDCS24
n
/f
R
XX
) as the operation clock). For detail, refer to CHAPTER
Note
is selected and the clock can be stopped in the
WDCS23
Note
WDCS22
WDCS21
WDCS20
491
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