UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 259

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TPnIOC0
TPnIOC2
(c) TMPn I/O control register 0 (TPnIOC0)
(d) TMPn I/O control register 2 (TPnIOC2)
(e) TMPn counter read buffer register (TPnCNT)
(f) TMPn capture/compare register 0 (TPnCCR0)
(g) TMPn capture/compare register 1 (TPnCCR1)
Note The TPnEES1 and TPnEES0 bits can only be set to 1 when the timer output (TOPn1) is used.
The value of the 16-bit counter can be read by reading this register.
If the TPnCCR0 register is set to D
Interval = (D
Usually, the TPnCCR1 register is not used in the interval timer mode. However, because the set value of
the TPnCCR1 register is transferred to the CCR1 buffer register and a compare match interrupt request
signal (INTTPnCC1) is generated when the value of the 16-bit counter matches the value of the CCR1
buffer register, interrupts from this register must be masked by setting the interrupt mask flag
(TPnCCMK1).
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not
0
0
Note that when setting these bits to 1, the TPnCCR0 and TPnCCR1 registers must be set to the
same value (that is, the same value as the value already specified for these registers).
2. n = 0 to 5
0
+ 1) × Count clock cycle
used in the interval timer mode.
0
0
Figure 7-8. Register Settings in Interval Timer Mode (2/2)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
0
0
0
User’s Manual U18953EJ5V0UD
0
0
, the interval is as follows:
TPnOL1
TPnEES1
0/1
0/1
Note
TPnOE1 TPnOL0
TPnEES0 TPnETS1 TPnETS0
0/1
0/1
Note
0/1
0
TPnOE0
0/1
0
0: Disable TOPn0 pin output.
1: Enable TOPn0 pin output.
Output level when TOPn0 pin
is disabled:
0: Low level
1: High level
0: Disable TOPn1 pin output.
1: Enable TOPn1 pin output.
Output level when TOPn1
pin is disabled:
0: Low level
1: High level
These bits select the valid
edge of the external event
count input (TIPn0 pin).
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