UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 674

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UPD70F3738GF-GAS-AX

Manufacturer Part Number
UPD70F3738GF-GAS-AX
Description
MCU 32BIT V850ES/JX3-L 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Lr
Datasheet

Specifications of UPD70F3738GF-GAS-AX

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3738GF-GAS-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
18.6.14 Clock timing
672
Notes 1. The INTCBnT interrupt is set when the data written to the CBnTX register is transferred to the data
Caution In single transfer mode, writing to the CBnTX register with the CBnTSF bit set to 1 is ignored.
2. The INTCBnR interrupt occurs if reception is complete and the next receive data is ready in the
SIBn capture
SCKBn pin
SOBn pin
Reg-R/W
INTCBnT
interrupt
INTCBnR
interrupt
CBnTSF bit
SCKBn pin
SIBn capture
SOBn pin
Reg-R/W
INTCBnT
interrupt
INTCBnR
interrupt
CBnTSF bit
shift register in the continuous transmission or continuous transmission/reception mode. In the
single transmission or single transmission/reception mode, the INTCBnT interrupt request signal is
not generated, but the INTCBnR interrupt request signal is generated at the end of communication.
CBnRX register while reception is enabled. In the single mode, the INTCBnR interrupt request
signal is generated even in the transmission mode, at the end of communication.
This has no effect on the operation during transfer.
Note 1
Note 2
Note 1
Note 2
(ii) Communication type 3 (CBnCKP and CBnDAP bits = 10)
(i) Communication type 1 (CBnCKP and CBnDAP bits = 00)
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
Figure 18-30. Clock Timing (1/2)
D7
D7
User’s Manual U18953EJ5V0UD
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0

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