UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 624

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

622
(5) Allowable baud rate range during reception
The baud rate error range at the destination that is allowable during reception is shown below.
Caution The baud rate error indicated below is a theoretical value. In practice, the signal might be
As shown in Figure 17-16, the receive data latch timing is determined by the counter set using the UC0CTL2
register following start bit detection. The transmit data can be received normally if up to the last data (stop bit)
can be received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
Maximum allowable
Minimum allowable
data frame length
data frame length
data frame length
BL = (Brate)
Minimum allowable data frame length: FLmin = 11 × BL −
Brate: UARTC0 baud rate (n = 0 to 2)
k:
BL:
FL:
Latch timing margin: 2 clock cycles
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
UARTC0
distorted, or communication might not be performed normally even if the error is within the
allowable range. Therefore, the error must be minimized.
Setting value of UC0CTL2.UC0BRS7 to UC0CTL2.UC0BRS0 bits (n = 0 to 2)
1-bit data length
Length of 1 data frame
−
1
Figure 17-16. Allowable Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
Bit 0
User’s Manual U18953EJ5V0UD
Bit 0
BL
Bit 0
Bit 1
Bit 1
Bit 1
1 data frame (11 × BL = FL)
FLmin
k − 2
2k
FLmax
Bit 7
× BL =
Bit 7
Bit 7
21k + 2
PD70F3792, 70F3793)
Parity bit
Parity bit
2k
Parity bit
BL
Stop bit
Stop bit
Stop bit