UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 786

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
784
Reset
Non-
maskable
Software
exception
Exception
trap
Maskable
Notes 1. The software that generated the exception event can be checked using the exception code set to the
Type
2. n = 0 to FH
Default
Priority
EICC bit of the ECR register.
10
11
12
13
14
15
16
17
18
19
20
21
22
−
−
−
−
−
−
0
1
2
3
4
5
6
7
8
9
RESET
NMI
INTWDT2
TRAP0n
TRAP1n
ILGOP/
DBG0
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
INTTQ0OV
INTTQ0CC0 TMQ0 capture 0/compare 0 match
INTTQ0CC1 TMQ0 capture 1/compare 1 match
INTTQ0CC2 TMQ0 capture 2/compare 2 match
INTTQ0CC3 TMQ0 capture 3/compare 3 match
INTTP0OV
INTTP0CC0 TMP0 capture 0/compare 0 match
INTTP0CC1 TMP0 capture 1/compare 1 match
INTTP1OV
INTTP1CC0 TMP1 capture 0/compare 0 match
INTTP1CC1 TMP1 capture 1/compare 1 match
INTTP2OV
INTTP2CC0 TMP2 capture 0/compare 0 match
INTTP2CC1 TMP2 capture 1/compare 1 match
CHAPTER 21 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
Name
Note 2
Note 2
RESET pin input
Reset input by internal source
TRAP instruction
TRAP instruction
Illegal opcode/
DBTRAP instruction
NMI pin valid edge input
WDT2 overflow
Low voltage detection
External interrupt pin input edge
detection (INTP0)
External interrupt pin input edge
detection (INTP1)
External interrupt pin input edge
detection (INTP2)
External interrupt pin input edge
detection (INTP3)
External interrupt pin input edge
detection (INTP4)
External interrupt pin input edge
detection (INTP5)
External interrupt pin input edge
detection (INTP6)
External interrupt pin input edge
detection (INTP7)
TMQ0 overflow
TMP0 overflow
TMP1 overflow
TMP2 overflow
Table 21-1. Interrupt Source List (1/3)
User’s Manual U18953EJ5V0UD
Trigger
RESET
Pin
WDT2
POCLVI
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
TMQ0
TMQ0
TMQ0
TMQ0
TMQ0
TMP0
TMP0
TMP0
TMP1
TMP1
TMP1
TMP2
TMP2
TMP2
Generating
Unit
−
−
−
0000H
0010H
0020H
004nH
005nH
0060H
0080H
0090H
00A0H
00B0H
00C0H
00D0H
00E0H
00F0H
0100H
0160H
0190H
01C0H
Exception
0110H
0120H
0130H
0140H
0150H
0170H
0180H
01A0H
01B0H
01D0H
01E0H
Code
Note 2
Note 2
00000000H
00000010H
00000020H
00000040H
00000050H
00000060H
00000080H
00000090H
000000A0H
000000B0H
000000C0H
000000D0H
000000E0H
000000F0H
00000100H
00000110H
00000120H
00000130H
00000140H
00000150H
00000160H
00000170H
00000180H
00000190H
000001A0H
000001B0H
000001C0H
000001D0H
000001E0H
Address
Handler
LVIIC
PIC0
PIC1
PIC2
PIC3
PIC4
PIC5
PIC6
PIC7
TQ0OVIC
TQ0CCIC0
TQ0CCIC1
TQ0CCIC2
TQ0CCIC3
TP0OVIC
TP0CCIC0
TP0CCIC1
TP1OVIC
TP1CCIC0
TP1CCIC1
TP2OVIC
TP2CCIC0
TP2CCIC1
Interrupt Control
Register
−
−
−
−
−
−