IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 100

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–62
PCI Express Compiler User Guide
rx_req0
(1)
rx_desc
(1)
Table 3–27. Standard Descriptor Phase Signals (Part 1 of 2)
,
,
(2)
(2)
Signal
n
[135:0]
O
O
I/O
1
Table 3–27
Receive request. This signal is asserted by the MegaCore function to request a
packet transfer to the application interface. It is asserted when the first two
DWORDS of a transaction layer packet header are valid. This signal is asserted
for a minimum of two clock cycles and
cannot be asserted at the same time as this signal. The complete descriptor is
valid on the second clock cycle that this signal is asserted.
Receive descriptor bus. Bits (125:0) have the same meaning as a standard
transaction layer packet header as defined by the PCI Express Base
Specification Revision 1.0a. Byte 0 of the header occupies bits 127:120 of the
rx_desc
15 in bits 7:0. See
header formats.
For bits 135:128 (descriptor and BAR decoding), see
transactions received by an endpoint do not have any bits asserted and must be
routed to the master block in the application layer.
rx_desc[127:64]
is asserted, allowing precoding and arbitrating to begin as quickly as possible.
The other bits of rx_desc are not valid until the following clock cycle as shown in
the following diagram.
Bit 126 of the descriptor indicates the type of transaction layer packet in transit:
●
●
rx_desc[135:128]
rx_desc[127:64]
rx_desc[63:0]
rx_desc[126]
rx_desc[126]
PCI Express Compiler Version 6.1
rx_ack
rx_req
In the following tables, transmit interface signal names suffixed
with 0 are for virtual channel 0. If the MegaCore function
implements additional virtual channels, there are an additional
set of signals suffixed with the virtual channel number.
bus, byte 1 of the header occupies bits 119:112, and so on, with byte
describes the standard descriptor phase signals.
1
X
X
X
Appendix B, Transaction Layer Packet Header Formats
2
set to 0: transaction layer packet without data
set to 1: transaction layer packet with data
begins transmission on the same clock cycle that
Valid
Clock Cycles
3
Valid
Valid
4
Description
5
X
X
X
rx_abort
6
,
rx_retry
Table
3–28. Completion
Altera Corporation
, and
December 2006
rx_ack
rx_req
for the