IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 155

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Simple DMA
Example Design
Altera Corporation
December 2006
This example design shows how to create an endpoint application layer
design that interfaces to the PCI Express MegaCore function. The design
includes the following:
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The example endpoint design is completely contained within a supported
Altera device and relies on no other hardware interface than the PCI
Express link. This allows you to use the example design for the initial
hardware validation of your system.
The Quartus II software generates the example design in the same
language that you used for the variation (generated by the variation name
file); the example design is either Verilog HDL or VHDL.
When the MegaWizard interface generates the MegaCore variant, the
example endpoint design is created with the MegaCore function
variation. The example design includes two main components, the
MegaCore function variation and an application layer example design as
shown in
page
The example endpoint design application layer provides these features:
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The example endpoint design can be used in the testbench simulation and
to compile a complete design for an Altera device. All of the modules
necessary to implement the example design with the variation file are
contained in separate files, based on the language you use:
<variation name>_example_top.vhd
<variation name>_example_top.v
altpcierd_dprambe.v or altpcierd_dprambe.vhd
Memory that can be a target for PCI Express memory read and write
transactions.
A DMA channel that can initiate memory read and write transactions
on the PCI Express link.
Shows you how to interface to the PCI Express MegaCore function
Target memory that can be written to and read from PCI Express
memory write and read transactions
DMA channel that can be used to initiate memory read and write
transactions on the PCI Express link
Master memory block that can be used to source and sink data for
DMA initiated memory transactions
Data pattern generator that can be used to source data for DMA
initiated memory write transactions
Support for two virtual channels (VCs)
5–6.
PCI Express Compiler Version 6.1
“Top-Level Simple DMA Example Design for Simulation” on
PCI Express Compiler User Guide
5–5