IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 105

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Retried Transaction & Masked Non-Posted Transactions
When the application layer can no longer accept non-posted requests, one
of two things happen: either the application layer requests the packet be
resent or it asserts rx_mask. For the duration of rx_mask, the MegaCore
function masks all non-posted transactions and reprioritizes waiting
transactions in favor of posted and completion transactions. When the
application layer can once again accept non-posted transactions,
rx_mask is deasserted and priority is given to all non-posted
transactions that have accumulated in the receive buffer.
Each virtual channel has a dedicated data path and associated buffers,
and no ordering relationships exist between virtual channels. While one
virtual channel may be temporarily blocked, data flow continues across
other virtual channels without impact. Within a virtual channel,
reordering is mandatory only for non-posted transactions to prevent
deadlock. Reordering is not implemented in the following cases:
■
■
■
In
transaction of 4 DWORDS that it cannot immediately accept. A second
transaction (memory write transaction of 1 DWORD) is waiting in the
receive buffer. Bit 2 of rx_data[63:0] for the memory write request is set to
1.
In clock cycle 3, transmission of non-posted transactions is not permitted
for as long as rx_mask is asserted.
Flow control credits are updated only after a transaction layer packet has
been extracted from the receive buffer and both the descriptor phase and
data phase (if any) have ended. This update happens in clock cycles 8 and
12 in
Figure
Between traffic classes mapped in the same virtual channel
Between posted and completion transactions
Between transactions of the same type regardless of the relaxed-
ordering bit of the transaction layer packet
Figure
PCI Express Compiler Version 6.1
3–25, the MegaCore function receives a memory read request
3–25.
PCI Express Compiler User Guide
3–67