IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 246

IP CORE Renewal Of IP-PCIE/8

IPR-PCIE/8

Manufacturer Part Number
IPR-PCIE/8
Description
IP CORE Renewal Of IP-PCIE/8
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-PCIE/8

Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x8 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
Test-Out Interface Signals for x1 and x4 MegaCore Functions
C–16
PCI Express Compiler User Guide
err_deskew
rdusedw0
rxstatus0
rxpolarity0
rdusedw1
Table C–1. test_out Signals for the x1 and x4 MegaCore Functions (Part 15 of 17)
Signal
MAC
deskew
Subblock
PCS0
PCS0
PCS0
PCS1
447:440
451:448
454:452
455
459:456
PCI Express Compiler Version 6.1
Bit
Deskew FIFO error. This signal indicates whether a deskew
error (deskew FIFO overflow) has been detected on a particular
physical lane. In such a case, the error is considered a receive
port error and retraining of the link is initiated.
The 4 MSBs are hard-wired to zero.
Elastic buffer counter 0. This signal indicates the number of
symbols in the elastic buffer.
Monitoring the elastic buffer counter of each lane can highlight
the PPM between the receive clock and transmit clock as well
as the skew between lanes. Not meaningful when using the
generic PIPE PHY interface.
PIPE rxstatus 0
detected and reported on a per lane basis. For example:
Not meaningful when using the generic PIPE PHY interface.
PIPE polarity inversion 0
LTSSM requires the PCS subblock to invert the polarity of the
received 10-bit data during training.
Elastic buffer counter 1. This signal indicates the number of
symbols in the elastic buffer.
Monitoring the elastic buffer counter of each lane can highlight
the PPM between the receive clock and transmit clock as well
as the skew between lanes. Not meaningful when using the
generic PIPE PHY interface.
000: Receive data OK
001: 1 SKP added
010: 1 SKP removed
011: Receiver detected
100: 8B/10B decode error
101: Elastic buffer overflow
110: Elastic buffer underflow
111: Running disparity error
. This signal is used to monitor errors
Description
. When asserted, the
Altera Corporation
December 2006

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