IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 168

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chaining DMA Example Design
5–18
PCI Express Compiler User Guide
MSI Number
MSI Traffic
Class
BDT
Upper DWORD
BDT
Lower DWORD
EPLAST_ENA
RCLAST
Table 5–7. Chaining DMA Descriptor Header Fields (Part 2 of 2)
Header Field
Descriptor
R
R
R
R
R
R
Access
EP
R/W
R/W
R/W
R/W
R/W
R/W
Access
RC
0x00 (DMA write)
0x10 (DMA read)
0x00 (DMA write)
0x10 (DMA read)
0x04 (DMA write)
0x14 (DMA read)
0x08 (DMA write)
0x18 (DMA read)
0x00 (DMA write)
0x10 (DMA read)
0x0C (DMA write)
0x1C (DMA read)
PCI Express Compiler Version 6.1
EP Address
When your RC reads the MSI capabilities of the EP,
these register bits map to the PCI Express back-end
MSI signals
If there is more than one MSI, the default mapping if
all the MSIs are available, is:
MSI 0 = Read
MSI 1 = Write
When the RC application software reads the MSI
capabilities of the EP, this value is assigned by
default to MSI traffic class 0. These register bits
map to the PCI Express back-end signal
app_msi_tc
Base Address Descriptor table address
Base Address Descriptor table address
Enables EPLAST logic across all descriptors
Enables memory polling across all descriptors.
When this bit is set, the EP DMA module issues a
memory write to the BFM shared memory to report
the number of DMA descriptors completed. Your
software application can poll this memory location to
monitor the DMA transfer status.
RCLAST reflects the number of descriptors ready to
be transferred. Your software application can
periodically update this register based on system
level memory scheduling constraints.
app_msi_num
[2:0}
Description
[4:0].
Altera Corporation
December 2006