IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 175

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Altera Corporation
December 2006
Descriptor Header for DMA Write
DW0
DW1
DW2
DW3
Table 5–14. Descriptor Header for DMA Write
0x0
0x4
0x8
0xc
Offset in EP Memory
2.
After writing the last DWORD of the Descriptor header (DW3), the DMA
write starts the three subsequent data transfers
3.
DMA Read Cycles
The procedure dma_rd_test used for DMA reads uses the following
three steps:
1.
2.
3.
Set up the chaining DMA descriptor header and starts the transfer
data from the EP memory to the BFM shared memory. This is done
by a call to the procedure dma_set_header which writes the
following four DWORDS into the DMA write register module:
Wait for the DMA write completion by polling the BFM share
memory location 0x80c, where the DMA write engine is updating
the value of the number of completed DMA. This is done by a call to
the procedure rcmem_poll.
Configure the BFM shared memory. This is done by a call to the
procedure dma_set_rd_desc_data which sets three descriptors
tables with the content shown below:
Set up the chaining DMA descriptor header and start the transfer
data from the EP memory to the BFM shared memory. This is done
by a call to the procedure dma_set_header which writes the
following four DWORDS into the DMA write register module:
After writing the last DWORD of the Descriptor header (DW3), the
DMA write starts the three subsequent data transfers.
Wait for the DMA write completion by polling the BFM share
memory location 0x90c, where the DMA write engine is updating
the value of the number of completed DMA. This is done by a call to
the procedure rcmem_poll.
PCI Express Compiler Version 6.1
3
0
0x800
2
Value
Number of descriptors and control bits (as described in
Table 5–5 on page
BFM shared memory upper address value
BFM shared memory lower address value
Last descriptor written
5–17)
PCI Express Compiler User Guide
Description
5–25