IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 98

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
Figure 3–22. Multiple Wait States that Throttle Data Transmission Waveform
3–60
PCI Express Compiler User Guide
Descriptor
Signals
Signals
Data
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
Multiple Wait States Throttle Data Transmission
In this example, the application transmits a 32-bit memory write
transaction. Address bit 2 is set to 0. See
inserted during the first two data phases because the MegaCore function
implements a small buffer to give maximum performance during
transmission of back-to-back transaction layer packets.
In clock cycles 5, 7, 9, and 11, the MegaCore function inserts wait states to
throttle the flow of transmission.
1
X
X
PCI Express Compiler Version 6.1
2
MEMWR64
3
DW1
DW0
4
DW3
DW2
5
DW5
DW4
6
Clock Cycles
7
DW7
DW6
8
9
DW9
DW8
10
Figure
11
DW11
DW10
3–22. No wait states are
12
13
Altera Corporation
14
December 2006
X
X
15