IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 159

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench & Example Designs
Altera Corporation
December 2006
0x00
0x04
0x08
0x0C
0x0C
(offset from BAR2,3)
Table 5–3. Example Design Control Registers (Part 1 of 2)
Register Byte
Address
31:0
31:0
31:0
All
31
30:23
22
21
20
19
18:16
15
14
Field
Bit
4.
5.
DMA channel PCI Express address[31:0] —These are the lower 32 bits of the
DMA channel operation size — This register specifies the length in bytes of the
DMA channel control register. Writing to any byte in this register starts a DMA
Specifies the maximum payload size for DMA channel transactions — This can
starting address used for memory transactions created by the DMA channel.
DMA channel PCI Express Address[63:32] —These are the upper 32 bits of the
starting address used for memory transactions created by the DMA channel.
DMA operation to perform.
operation.
DMA channel operation in progress —This is the read-only bit. When this bit is
set to 1 a DMA operation is in progress.
Reserved.
DMA channel uses an incrementing DWORD pattern for memory write
transactions.
DMA channel uses an incrementing byte pattern for memory write transactions.
DMA channel uses all zeros as the data for memory write transactions.
Reserved.
be used to restrict the DMA channel to using smaller transactions than allowed
by the configuration space Max Payload Size and Max Read Request Size. The
transaction size is the smallest allowed. This uses the same encoding as those
fields:
Sets value of the TD bit in all PCI Express request headers generated by this
DMA channel operation. The TD bit is the TLP digest field present bit.
Sets value of the EP bit in all PCI Express request headers generated by this
DMA channel operation. The EP bit is the poisoned data bit.
Writing the attributes (including PCI Express memory write or read
direction) of the requested operation to the register at offset 0x0C.
Writing to this register starts the execution of the DMA channel
operation.
Reading the DMA channel operation in progress bit at offset 0x0C to
determine when the DMA channel operation has completed.
000—128 Bytes
001—256 Bytes
010—512 Bytes
011—1 KBytes
100—2 KBytes
PCI Express Compiler Version 6.1
Description
PCI Express Compiler User Guide
5–9