IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 50

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Functional Description
3–12
PCI Express Compiler User Guide
Figure
the Flow Control Update loop. In
PCI Express ports:
■
■
As the PCI Express specification describes, each Transmitter, the Write
Requester in this case, maintains a Credit Limit register and Credits
Consumed register. The Credit Limit register is the sum of all credits
issued by the Receiver, the Write Completer in this case. The Credit Limit
register is initialized during the flow control initialization phase of link
initialization and then updated during operation by Flow Control (FC)
Update DLLPs. The Credits Consumed register is the sum of all credits
consumed by packets transmitted. Separate Credit Limit and Credits
Consumed registers exist for each of the six types of Flow Control:
■
■
■
■
■
■
Each Receiver also maintains a Credit Allocated counter which is
initialized to the total available space in the Rx Buffer (for the specific
Flow Control class) and then incremented as packets are pulled out of the
Rx Buffer by the application layer. The value of this register is sent as the
FC Update DLLP value.
Write Requester
Write Completer
Posted Headers
Posted Data
Non-Posted Headers
Non-Posted Data
Completion Headers
Completion Data
PCI Express Compiler Version 6.1
3–5, Flow Control Update Loop, shows the main components of
Figure
3–5, you see two communicating
Altera Corporation
December 2006