IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 110

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–72
PCI Express Compiler User Guide
rx_req
rx_req
rx_req
rx_retry
Table 3–30. Minimum & Maximum Latency Values in Clock Cycles Between Receive Signals
Signal 1
rx_ack
rx_dfr
rx_dv
rx_req
Signal 2
Dependencies Between Receive Signals
Table 3–30
cycles between various receive signals.
Clocking
The Altera PCI Express MegaCore functions use one of several possible
clocking configurations, depending on the PHY (generic PIPE or
Stratix GX) and the reference clock frequency. The functions have two
clock input signals, refclk and clk125_in.
The functions also have an output clock, clk125_out, that is a 125-MHz
transceiver clock. In Stratix GX PHY implementations, clk125_out is a
125-MHz version of the transceiver reference clock and must be used to
generate clk125_in. In generic PIPE PHY implementations, this signal
is driven from the refclk input.
■
■
1
1
0
1
1
Min Typical Max
refclk–This signals provides the reference clock for the transceiver
for Stratix GX PHY implementations. For generic PIPE PHY
implementations, refclk is driven directly to clk125_out.
clk125_in–This signal is the clock for all of the function’s registers,
except for a small portion of the receive PCS layer that is clocked by
a recovered clock in Stratix GX PHY implementations. All
synchronous application layer interface signals are synchronous to
this clock. clk125_in must be 125 MHz and in Stratix GX PHY
implementations it must be the exact same frequency as
clk125_out. In generic PIPE PHY implementations, it must be
connected to the pclk signal from the PHY.
1
0
1-2
2
PCI Express Compiler Version 6.1
Implementing the x4 MegaCore function in Stratix GX devices
uses 4 additional clock resources for the recovered clocks on a
per lane basis. The PHY layer elastic buffer uses these clocks.
describes the minimum and maximum latency values in clock
N
0
N
N
Always asserted on the same clock cycle if a data payload
is present, except when a previous data transfer is still in
progress. See
Assuming data is sent.
rx_req
refers to the next transaction request.
Figure 3–27 on page
Notes
3–70.
Altera Corporation
December 2006