IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 217

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration
Signals for x1
and x4
MegaCore
Functions
Altera Corporation
December 2006
k_gbl[0]
k_gbl[9:1]
k_gbl[10]
k_gbl[11]
k_gbl[15:12]
k_gbl[25:16]
k_gbl[26]
k_gbl[31:27]
k_conf[15:0]
k_conf[31:16]
k_conf[39:32]
k_conf[63:40]
k_conf[79:64]
k_conf[95:80]
k_conf[98:96]
Table A–1. Configuration Signals for x1 and x4 MegaCore Functions (Part 1 of 6)
Signal
Fixed to 0
Fixed to 0
Capabilities: Link
Common Clock
Fixed to 0
System: Interface Type
Fixed to 0
Fixed to 1
Fixed to 0
Capabilities: Vendor ID
Capabilities: Device ID
Capabilities: Revision ID
Capabilities: Class Code
Capabilities: Subsystem
Vendor ID
Capabilities: Subsystem
Device ID
Fixed to 0b010
Table A–1
signals for x1 and x4 MegaCore functions. These signals are set internal to
the variation file created by the Quartus II software. They should not be
modified except by MegaWizard interface. They are provided here for
reference.
Value or Wizard
Page/Label
PCI Express Compiler Version 6.1
shows all of the MegaCore function’s available configuration
PCI Express specification compliance setting. When
the value is set to 1, the MegaCore function is set to be
compliant with the PCI Express 1.1 specification.
When the value is set to 0, the MegaCore function is set
to be compliant with PCI Express 1.0a specification.
Reserved.
Clock configuration, 0 = system reference clock not
used, 1 = system reference clock used for PHY.
Reserved.
Port type: 0 = native EP, 1 = legacy EP.
Reserved.
Implement reordering on receive path.
Reserved.
Vendor ID register.
Device ID register.
Revision ID register.
Class code register.
Subsystem vendor ID register.
Subsystem device ID register.
Power management capabilities register version field
(set to 010).
Configuration Signals
Description
Appendix A.
A–1