IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 15

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

About This Compiler
Altera Corporation
December 2006
Testbench & Example Designs: Simple DMA and Chaining DMA
The PCI Express Compiler includes an endpoint testbench that
incorporates a basic root port bus functional model (BFM) and two
endpoint design examples: simple DMA and chaining DMA. Both
endpoint design examples illustrate the application interface to the PCI
Express MegaCore function and are delivered as clear-text source-code
(VHDL and Verilog HDL) suitable for both simulation and synthesis, as
well as OpenCore Plus evaluation of the MegaCore function in hardware.
The basic root port BFM incorporates a driver and an IP functional
simulation model of a root port.
testbench setup for the simple DMA example.
testbench for the chaining DMA example.
Figure 1–2. Testbench for the Simple DMA Example
PCI Express Compiler Version 6.1
Endpoint Simple DMA Example
Endpoint Application
Layer Example
(32 KBytes)
Memory
Control
Target
Target
Traffic Control/Virtual Channel Mapping
Root Port BFM
Request/Completion Routing
x8 Root Port Model
Root Port Driver
MegaCore Function
Figure 1–2
PCI Express
Registers
Control
DMA
PCI Express Link
User Interface
User Interface
PCI Express Compiler User Guide
illustrates the endpoint
Figure 1–3
(32 KBytes)
Memory
Control
DMA
DMA
illustrates the
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