IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 152

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–2
PCI Express Compiler User Guide
The Altera testbench and root port BFM provide a simple method to do
basic testing of the application layer logic that interfaces to the MegaCore
function endpoint variation. However, the testbench and root port BFM
are not intended to be a substitute for a full verification environment. To
thoroughly test your application, Altera suggests that you obtain
commercially available PCI Express verification IP and tools, and/or do
your own extensive hardware testing.
Your application layer design may need to handle at least the following
scenarios that are not possible to create with the Altera testbench and the
root port BFM. The Altera root port BFM has the following limitations:
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The simple and chaining DMA example designs provided with the core
are designed to handle all of the above behaviors, even though the
provided testbench cannot test them.
Additionally PCI Express link monitoring and error injection capabilities
are limited to those provided by the MegaCore function’s test_in and
test_out signals. The testbench and root port BFM will not NAK any
transactions.
It is unable to generate or receive vendor defined messages. Some
systems generate vendor defined messages and the application layer
must be designed to process them. The MegaCore function passes
these messages on to the application layer which in most cases
should ignore them, but in all cases must issue an rx_ack to clear the
message from the Rx buffer.
It can only handle received read requests that are less than or equal
to the currently set max payload size. Many systems are capable of
handling larger read requests that are then returned in multiple
completions.
It always returns a single completion for every read request. Some
systems split completions on every 64-byte address boundary.
It always returns completions in the same order the read requests
were issued. Some systems will generate the completions out of
order.
It is unable to generate zero-length read requests that some systems
generate as flush requests following some write transactions. The
application layer must be capable of generating the completions to
the zero length read requests.
PCI Express Compiler Version 6.1
Altera Corporation
December 2006