IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 131

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Notes for
(1)
pipe_rstn
pipe_txclk
test_in[31:0]
test_out[511:0]
test_out[127:0]
Table 3–40. PIPE Interface Signals (Part 2 of 2)
Table 3–41. Test Interface Signals
where n is the lane number ranging from 0-7
Table 3–40
Signal
Signal
for x1 or x4
for x8
Test Signals
Table 3–40
O
O
I/O
I
O
I/O
Asynchronous reset to external phy. It is tied high and expects a pull-down
resistor on the board. During FPGA configuration, the pull-down resistor
will reset the phy and after that the FPGA will drive the phy out of reset.
This signal is only on MegaCore function configured for the external phy.
Transmit data path clock to external phy. This clock is derived from
refclk
data of the phy.
PCI Express Compiler Version 6.1
The
features as well as error injection capability. See
Interface Signals
bus. For normal operation this bus can be driven to all 0s.
The
of the MegaCore function. See
for a complete description of the individual bits in this bus. For normal
operation this bus can be left unconnected.
describes the available test signals.
test_out
test_in
and it provides the source synchronous clock for the transmit
bus provides run-time control for specific MegaCore
bus provides extensive monitoring of the internal state
for a complete description of the individual bits in this
Description
Description
Appendix C, Test Port Interface Signals
PCI Express Compiler User Guide
Appendix C, Test Port
3–93