IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 102

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–64
PCI Express Compiler User Guide
rx_ben[7:0]
(1)
rx_dfrn
(1)
rx_dvn
(1)
rx_datan[63:0]
(1)
rx_wsn
(1)
Table 3–29. Data Phase Signals (Part 1 of 2)
,
,
,
,
,
(2)
(2)
(2)
(2)
(2)
)
Signal
O
O
O
O
I
I/O
Receive byte enable. These signals qualify data on
the signal indicates whether the corresponding byte of data on
is valid. These signals are not available in the x8 MegaCore function.
Receive data phase framing. This signal is asserted on the same or subsequent
clock cycle as
needed). It is deasserted on the clock cycle preceding the last data phase to signal
to the application layer the end of the data phase. The application layer does not
need to implement a data phase counter.
Receive data valid. This signal is asserted by the MegaCore function to signify that
rx_data[63:0]
Receive data bus. This bus transfers data from the link to the application layer. It is
2 DWORDS wide and is naturally aligned with the address in one of two ways,
depending on bit 2 of
●
●
●
●
This natural alignment allows you to connect
data path aligned on a QW address (in the little endian convention).
Bit 2 is set to 1 (5 DWORD transaction)
Bit 2 is set to 0 (5 DWORD transaction)
Receive wait states. With this signal, the application layer can insert wait states to
throttle data transfer.
rx_data[63:32]
rx_data[63:32]
Table 3–29
rx_data[31:0]
rx_data[31:0]
rx_desc[2]
rx_data[31:0]
rx_desc[34]
rx_data[31:0]
rx_desc[2]
rx_data[63:32]
rx_desc[34]
rx_data[63:32]
PCI Express Compiler Version 6.1
describes the data phase signals.
1
1
rx_req
X
X
X
X
2
2
(64-bit address) set to 0: The first DWORD is located on
(64-bit address) set to 1: The first DWORD is located on bits
contains data.
(32-bit address) set to 0: The first DWORD is located on bits
(32-bit address) set to 1: The first DWORD is located on bits
rx_desc
.
.
Clock Cycles
Clock Cycles
3
3
.
.
to request a data phase (assuming a data phase is
DW 0
DW 0
DW 1
4
4
DW 3
DW 2
DW 2
DW 1
.
5
5
DW 4
DW 3
DW 4
Description
6
6
X
X
X
X
rx_data[63:0]
rx_data[63:0]
Altera Corporation
rx_data[63:0]
directly to a 64-bit
December 2006
. Each bit of