IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 248

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Test-Out Interface Signals for x1 and x4 MegaCore Functions
C–18
PCI Express Compiler User Guide
rdusedw3
rxstatus3
rxpolarity3
Reserved
Table C–1. test_out Signals for the x1 and x4 MegaCore Functions (Part 17 of 17)
Signal
Subblock
PCS3
PCS3
PCS3
PCS4
475:472
478:476
479
511:480
PCI Express Compiler Version 6.1
Bit
Elastic buffer counter 3. This signal reports the number of
symbols in the elastic Buffer.
Monitoring the elastic buffer counter of each lane can highlight
the PPM between the receive clock and transmit clock as well
as the skew between lanes. Not meaningful when using the
generic PIPE PHY interface.
PIPE rxstatus 3
detected and reported on a per lane basis. For example:
●
●
●
●
●
●
●
●
Not meaningful when using the generic PIPE PHY interface.
PIPE polarity inversion 3
LTSSM requires the PCS subblock to invert the polarity of the
received 10-bit data during training. Not meaningful when using
the generic PIPE PHY interface.
Reserved.
000: receive data OK
001: 1 SKP added
010: 1 SKP removed
011: Receiver detected
100: 8B/10B decode error
101: Elastic buffer overflow
110: Elastic buffer underflow
111: Running disparity error
. This signal is used to monitor errors
Description
. When asserted, the
Altera Corporation
December 2006