IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 154

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench
5–4
PCI Express Compiler User Guide
PIPE_MODE
NUM_CONNECTED_LANES
FAST_COUNTERS
Table 5–1. Testbench VHDL Generics /Verilog HDL Parameters
Generic/Parameter
■
In addition, the testbench has routines that perform the following tasks:
The testbench has several VHDL generics/Verilog HDL parameters that
control the overall operation of the testbench. These generics are
described in
0 or 1
1,2,4,8
0 or 1
Allowed
Values
altpcietb_bfm_driver—This module drives transactions to the root
port BFM. This is the module that you modify to vary the
transactions sent to the example endpoint design or your own
design. For more information about this module, see
Driver Module For Simple DMA Example Design” on page
●
●
PCI Express Compiler Version 6.1
Generate the reference clock for the endpoint at the required
frequency
Provide a PCI Express reset at start up.
1
8
1
Default
Table
Value
5–1.
Controls whether the PIPE interface
or serial interface
simulation. The PIPE interface typically simulates much
faster than the serial interface. If the variation name file
only implements the PIPE interface, then setting
PIPE_MODE
always is used.
This controls how many lanes are interconnected by the
testbench. Setting this generic value to a lower number
simulates the endpoint operating on a narrower PCI
Express interface than the maximum.
If your variation only implements the x1 MegaCore
function, then this setting has no effect and only one lane
is used.
Setting this parameter to a 1 speeds up simulation by
making many of the timing counters in the PCI Express
MegaCore function operate faster than specified in the
PCI Express specification.This should usually be set to 1,
but can be set to 0 if there is a need to simulate the true
time-out values.
to 0 has no effect and the PIPE interface
(PIPE_MODE = 0
Description
(PIPE_MODE = 1)
Altera Corporation
) is used for the
“BFM Test
December 2006
5–20.