IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 122

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–84
PCI Express Compiler User Guide
pex_msi_num[4:0]
app_int_sts
Table 3–33. Interrupt Signals (Part 2 of 2)
Signal
I
I
I/O
Figure 3–38
Figure 3–38. MSI Handler Block
Figure 3–39
block with a per vector enable bit. A global application interrupt enable
can also be implemented instead of this per vector MSI.
Power management MSI number. This signal is used by power management
and/or hot plug to determine the offset between the base message interrupt
number and the message interrupt number to send through MSI.
Application interrupt status. This signal indicates the status of the application
interrupt. When asserted, an
maintained in the
PCI Express Compiler Version 6.1
illustrates the architecture of the MSI handler block.
illustrates a possible implementation of the MSI handler
int_status
app_msi_req
app_msi_ack
app_msi_tc
app_msi_num
pex_msi_num
app_int_sts
INT#
cfg_msicsr[31:0]
register.
Description
message is generated and the status is
MSI Handler
Block
Altera Corporation
December 2006