IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 49

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
The physical layer is itself subdivided by the PIPE Interface Specification
into two layers (bracketed horizontally in
■
■
The physical layer integrates both digital and analog elements. Intel
designed the PIPE interface to separate the MAC from the PHY. The
MegaCore function is compliant with the PIPE interface, allowing
integration with other PIPE-compliant external PHY devices.
The MegaCore function automatically instantiates a complete PHY layer
when targeting the Stratix GX/Stratix II GX device family.
Lane Initialization
Connected PCI Express components may not support the same number
of lanes. The x4 MegaCore function supports initialization and operation
with components that have 1, 2, or 4 lanes.
The x8 MegaCore function supports initialization and operation with
components that have 1, 4, or 8 lanes. Components with 2 lanes operate
with 1 lane.
Analyzing Throughput
Throughput analysis requires that you understand the Flow Control
Loop (see
Control Loop and issues that will help you improve throughput.
Throughput of Posted Writes
The throughput of Posted Writes is limited primarily by the Flow Control
Update loop shown in
Writes sources the data as quickly as possible and the completer of the
Writes consumes the data as quickly as possible, then the Flow Control
Update loop can be the biggest determining factor in Write throughput,
besides the actual bandwidth of the link.
Media Access Controller (MAC) Layer—The MAC layer includes the
link training and status state machine and the
scrambling/descrambling and multilane deskew functions.
PHY Layer—The PHY layer includes the 8B/10B encode/decode
functions, elastic buffering, and serialization/deserialization
functions.
PCI Express Compiler Version 6.1
Figure 3–5 on page
Figure 3–5 on page
3–13). This section discusses the Flow
PCI Express Compiler User Guide
Figure
3–13. If the requester of the
3–4):
3–11