IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 46

IP CORE Renewal Of IP-PCIE/8

IPR-PCIE/8

Manufacturer Part Number
IPR-PCIE/8
Description
IP CORE Renewal Of IP-PCIE/8
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-PCIE/8

Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x8 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
Functional Description
Figure 3–3. Data Link Layer
3–8
PCI Express Compiler User Guide
Packet Description & Data
Packet Description & Data
Towards Transaction Layer
Rx Transaction Layer
Tx Transaction Layer
Configuration Space
Tx Flow Control Credits
Rx Flow Control Credits
Transaction Layer
Packet Checker
Transaction Layer
Packet Generator
The data link layer has the following subblocks:
Retry Buffer
AckNack
Packets
Data Link Control and Management State Machine—This state machine
is synchronized with the physical layer’s LTSSM state machine and
is also connected to the configuration space registers. It initializes the
link and virtual channel flow control credits and reports status to the
configuration space. (Virtual channel 0 is initialized by default, as are
additional virtual channels if they have been physically enabled and
the software permits them.)
Power Management—This function handles the handshake to enter
low power mode. Such a transition is based on register values in the
configuration space and received PM DLLPs.
Data Link Layer Packet Generator and Checker—This block is associated
with the data link layer packet’s 16-bit CRC and maintains the
integrity of transmitted packets.
PCI Express Compiler Version 6.1
Generator
DLLP
Management
Function
Checker
Power
DLLP
Tx Arbitration
Data Link Control
& Management
State Machine
Towards Physical Layer
Rx Packets
Tx Packets
& Status
Control
Altera Corporation
December 2006
Transmit
Data Path
Receive
Data Path

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