IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 252

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Test-In Interface
Test-In Interface
C–22
PCI Express Compiler User Guide
count6
count7
err_deskew
test_sim
test_lpbk
test_discr
test_nonc_phy
test_boot
Table C–2. test_out Signals for the x8 MegaCore Functions (Part 4 of 4)
Table C–3. test_in Signals (Part 1 of 5)
Signal
Signal
MAC
deskew
MAC
deskew
MAC
deskew
MAC ltssm 0
MAC ltssm 1
MAC ltssm 2
MAC ltssm 3
CFGcfgchk 4
Subblock
Subblock
You must implement specific logic in order to use the error-injection
capabilities of the test_in port. For example, to force an LCRC error on
the next transmitted transaction layer packet, test_in[21] must be
asserted for 1 clock cycle when transmit txdl_sm,
(test_out[282:280]) is in a non-idle state.
Table C–3
PCI Express Compiler Version 6.1
116:114
119:117
127:120
Bit
describes test_in signals.
Bit
Simulation mode. This signal must be set to 1 to accelerate
MegaCore function initialization.
Loopback master. This signal must be set to 1 to direct the link to
loopback (in master mode). This bit is reserved on the x8
MegaCore function.
Descramble mode. This signal must be set to 1 during initialization
to disable data scrambling.
Force_rxdet mode. This signal can be set to 1 in cases where the
PHY implementation does not support the Rx Detect feature. The
MegaCore function always detects the maximum number of
receivers during the detect state, and only goes to compliance
state if at least one lane has the correct pattern. This signal is
forced internal to the MegaCore function for Stratix GX PHY
implementations.
Remote boot mode. When asserted, this signal disables the BAR
check if the link is not initialized and the boot is located behind the
component.
Deskew fifo count lane 6: This signal indicates the number
of Words in the deskew fifo for physical lane 6.
Deskew fifo count lane 7: This signal indicates the number
of Words in the deskew fifo for physical lane 7.
Deskew fifo error: This signal indicates whether a deskew
error (deskew fifo overflow) has been detected on a
particular physical Lane. In such a case, the error is
considered a Receive Port error and retraining of the Link
is initiated.
Description
Description
Altera Corporation
December 2006