IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 137

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHYs
Altera Corporation
December 2006
8-bit DDR Mode
The implementation of the 8-bit DDR mode shown in
included in the file <variation name>.v or <variation name>.vhd and
includes a PLL. The PLL inclock is driven by refclk (pclk from the
external PHY) and has the following 3 outputs:
■
■
■
An edge detect circuit is used to detect the relationships between the 125
MHz clock and the 250 MHz rising edge to properly sequence the 16-bit
data into the 8-bit output register.
A zero delay copy of the 125 MHz refclk. The zero delay PLL
output is used as the clk125_in for the core and clocks a double
data rate register for the incoming receive data.
A 250 MHz "early" output this is multiplied from the 125 MHz
refclk is early in relation to the refclk. The 250 MHz early clock
PLL output is used to clock an 8-bit SDR transmit data output
register. A 250 MHz single data rate register is used for the 125 MHz
DDR output because this allows the use of the SDR output registers
in the Cyclone II IOB. The early clock is required to meet the required
clock to out times for the common refclk for the PHY. You may
need to adjust the phase shift for your specific PHY and board
delays. To alter the phase shift, copy the PLL source file referenced in
your variation file from the <path>/ip/PCI Express Compiler/lib
directory to your project directory. Then use the MegaWizard Plug In
Manger in the Quartus II software to edit the PLL source file to set
the required phase shift. Then add the modified PLL source file to
your Quartus II project.
An optional 62.5 MHz TLP Slow clock is provided for x1
implementations.
PCI Express Compiler Version 6.1
PCI Express Compiler User Guide
Figure 4–3
is
4–5