IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 236

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Test-Out Interface Signals for x1 and x4 MegaCore Functions
C–6
PCI Express Compiler User Guide
r2c_ack
c2r_ack
rxbuf_busy
rxfc_updated
r2c_ack
c2r_ack
rxbuf_busy
rxfc_updated
Reserved
desc_sm
desc_val
data_sm
req_ro
Table C–1. test_out Signals for the x1 and x4 MegaCore Functions (Part 5 of 17)
Signal
TRN
rxvc2
TRN
rxvc3
TRN rxvc
TRN rxvc
TRN rxvc
TRN rxvc
Subblock
110:107
114:111
133:131
134
136:135
137
PCI Express Compiler Version 6.1
Bit
Receive VC2 status. Reports different events related to VC2:
●
●
●
●
Receive VC3 status. Reports different events
related to VC3:
●
●
●
●
All consecutive signals between bits 131 and 255 depend on
the virtual channel selected by the
Receive descriptor state machine. Receive descriptor state
machine encoding:
●
●
●
●
●
●
Receive bypass mode valid. This signal reports that bypass
mode is valid for the current received transaction layer packet.
Receive data state machine. Receive data state machine
encoding:
●
●
●
●
Receive reordering queue busy. This signal reports that
transaction layer packets are currently reordered in the
reordering queue (information extracted from the transaction
layer packet FIFO).
bit 0: transaction layer packet sent to
the configuration space
bit 1: transaction layer packet received
from configuration space
bit 2: Receive buffer not empty
bit 3: Receive flow control credits
updated
bit 0: Transaction layer packet sent to
the configuration space
bit 1: Transaction layer packet received
from configuration space
bit 2: Receive buffer not empty
bit 3: Receive flow control credits
updated
000: idle
001: desc0
010: desc1
011: desc2
100: desc_wt
others: reserved
00: idle
01: data_first
10: data_next
11: data_last
Description
test_in[31:29]
Altera Corporation
December 2006
input.