IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 71

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
Configure transceiver
block
Internal clock
BAR Table (BAR0)
BAR Table (BAR1)
BAR Table (BAR2)
BAR Table (BAR3)
BAR Table (BAR4)
BAR Table (BAR5)
BAR Table (EXP-ROM)
Table 3–17. System Settings Page Parameters (Part 2 of 2)
Parameter
Enable fast recovery
mode or Enable rate
match fifo
62.5, 125, 250 MHz
BAR type and size
BAR type and size
BAR type and size
BAR type and size
BAR type and size
BAR type and size
BAR type and size
MegaCore Function BAR Support
The x1 and x4 MegaCore functions support Memory Space BARs ranging
in size from 128 bytes to the maximum allowed by a 32-bit or 64-bit BAR.
The x8 MegaCore functions support Memory Space BARs from 4 KBytes
to the maximum allowed by a 32-bit or 64-bit BAR.
The x1 and x4 MegaCore functions in Legacy Endpoint mode support
I/O Space BARs sized from 16 Bytes to 4 KBytes. The x8 MegaCore
function only supports I/O Space BARs of 4 KBytes.
Value
PCI Express Compiler Version 6.1
Displays a dialog box that allows you to configure the
transceiver block. This option is valid only when you
select a Stratix II GX PHY. See
Figure 3–8
Specifies the frequency of the internal clock which is
based on the number of lanes and the selected PHY
type. This is also the frequency at which the application
layer interface of the core operates.
For x8 configurations, the internal clock is fixed at 250
MHz. For x4 configurations, the internal clock is fixed at
125 MHz. For x1 configurations in Stratix II GX, the
internal clock is fixed at 125 MHz. For other x1
configurations, the Internal Clock can be selected to be
either 62.5 MHz or 125 MHz.
BAR0 size and type mapping (I/O space, memory space,
prefetchable). BAR0 and BAR1 can be combined to form
a 64-bit BAR.
BAR1 size and type mapping (I/O space, memory space,
prefetchable).
BAR2 size and type mapping (I/O space, memory space,
prefetchable). BAR2 and BAR3 can be combined to form
a 64-bit BAR.
BAR3 size and type mapping (I/O space, memory space,
prefetchable).
BAR4 size and type mapping (I/O space, memory space,
prefetchable).
BAR5 size and type mapping (I/O space, memory space,
prefetchable). BAR4 and BAR5 can be combined to form
a 64-bit BAR.
Expansion ROM BAR size and type mapping (I/O space,
memory space, prefetchable).
for details on these available options.
PCI Express Compiler User Guide
Description
Table 3–18
and
3–33