IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 53

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
From decrement of Transmit Credit Consumed
counter to PCI Express Link (ns).
From PCI Express Link until packet is available
at Application Layer interface (ns).
From Application Layer draining packet to
generation and transmission of FC Update
DLLP on PCI Express Link (assuming no
arbitration delay) (ns).
From receipt of FC Update DLLP on the PCI
Express Link to updating of transmitter's Credit
Limit register (ns).
128
256
512
1024
2048
Table 3–1. FC Update Loop Delay Components For Stratix II GX
Table 3–2. Data Credits Required By Packet Size
Max Packet Size
Delay
Table
the delay components for the FC Update in which the PCI Express
MegaCore functions are used with a Stratix II GX device. These delay
components are the delays independent of the packet length. The total
delays in the loop are increased by the packet length.
Based on the above FC Update Loop delays and additional arbitration
and packet length delays,
credits that need to be advertised to cover the delay. The Rx Buffer needs
to be sized to support this number of credits to maintain full bandwidth.
The above credits assume that there are devices with PCI Express
MegaCore function and Stratix II GX delays at both ends of the PCI
Express Link. Some devices at the other end of the link could have smaller
or larger delays, which would affect the minimum number of credits
64
80
128
192
384
Min
3–1, “FC Update Loop Delay Components For Stratix II GX,” shows
PCI Express Compiler Version 6.1
x8 Function
96
112
160
256
384
60
124
60
116
Max
Min
x8 Function
56
80
128
192
384
68
168
68
160
Table 3–2
Max
Min
x4 Function
104
200
120
184
shows the number of flow control
80
96
128
192
384
Min
x4 Function
PCI Express Compiler User Guide
Max
120
248
136
232
Max
40
64
96
192
384
Min
272
488
216
424
x1 Function
Min
x1 Function
48
64
96
192
384
288
536
232
472
Max
Max
3–15