IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 140

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

External PHY Support
4–8
PCI Express Compiler User Guide
8-bit SDR Mode
The implementation of the 8-bit SDR mode is shown in
included in the file <variation name>.v or <variation name>.vhd and
includes a PLL. The PLL inclock is driven by refclk (pclk from the
external PHY) and has the following 3 outputs:
■
■
■
An edge detect circuit is used to detect the relationships between the 125
MHz clock and the 250 MHz rising edge to properly sequence the 16-bit
data into the 8-bit output register.
A 125 MHz output derived from the 250 MHz refclk used as the
clk125_in for the core and also to transition the incoming 8-bit data
into a 16-bit register for the rest of the logic.
A 250 MHz "early" output that is skewed early in relation to the refclk
that is used to clock an 8-bit SDR transmit data output register. The
early clock PLL output is used to clock the transmit data output
register. The early clock is required to meet the required clock to out
times for the common clock. You may need to adjust the phase shift
for your specific PHY and board delays. To alter the phase shift, copy
the PLL source file referenced in your variation file from the
<path>/ip/PCI Express Compiler/lib directory to your project
directory. Then use the MegaWizard Plug In Manger in the Quartus
II software to edit the PLL source file to set the required phase shift.
Then add the modified PLL source file to your Quartus II project.
An optional 62.5 MHz TLP Slow clock is provided for x1
implementations.
PCI Express Compiler Version 6.1
Altera Corporation
Figure 4–5
December 2006
and is