IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 55

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
128
256
512
1024
2048
4096
Table 3–3. Completion Data Space (in Credit units) to Cover Read Round Trip Delay
Max Packet Size
Assuming there is a PCI Express switch in the path between the read
requester and the read completer and assuming typical read completion
times for root ports,
required to cover the read round trip delay.
Note also that the Completions can be broken up into multiple
completions that are less than the Maximum Packet Size. To do this, there
needs to be more room for completion headers than the completion data
space divided by the maximum packet size. Instead, the room for headers
needs to be the completion data space (in bytes) divided by 64 because
this is the smallest possible Read Completion Boundary. Setting the
Desired performance for received completions to High on the Buffer
Setup page when using Parameter Settings in your MegaCore function
will configure the Rx Buffer with enough space to meet the above
requirements. You can adjust the Desired performance for received
completions up or down from the High setting to tailor the Rx Buffer size
to your delays and required performance.
An additional constraint is the amount of read request data that can be
outstanding at one time. This is limited by the number of header tag
values that can be issued by the application and the maximum read
request size that can be issued. The number of header tag values that can
be used is also limited by the PCI Express MegaCore function. For the x1
and x4 functions, you can specify up to 256 tags to be used, though
configuration software can restrict the application to use only 32 tags.
However, 32 tags should be enough.
In the x8 core case, the MegaCore function offers a maximum of 8 tags.
But PCI Express systems today allow a maximum read request size of 512
or more, even when the Max Payload Size is restricted to 128 Bytes. The
512-byte read requests equate to reads of 32 credits. Therefore, issuing
eight (tag limit) 512 Byte read requests consumes 256 data credits, which
is enough to keep the Read Request loop full and maximize the
throughput.
PCI Express Compiler Version 6.1
120
144
192
256
384
768
Table 3–3
x8 Function
Typical
shows the estimated completion space
96
112
160
256
384
768
x4 Function
PCI Express Compiler User Guide
Typical
56
80
128
192
384
768
x1 Function
Typical
3–17