IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 164

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chaining DMA Example Design
5–14
PCI Express Compiler User Guide
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The chaining DMA example design hierarchy consists of these
components:
Each DMA modules consists of these components:
<variation name>_example_pipen1b—This module is the top level of
the example endpoint design that you use for simulation. This
module is contained in the following files produced by the
MegaWizard interface:
<variation name>_example_chaining_top.vhd
<variation name>_example_chaining_top.v
This module provides both PIPE and serial interfaces for the
simulation environment. This module has two debug ports named
test_out and test_in (see
monitor and control internal states of the MegaCore function.
For synthesis the top level module is <variation
name>_example_chaining_top. This module instantiates the module
<variation name>_example_pipen1b and propagates only a small
sub-set of the test ports to the external I/Os. These test ports can be
used in your design.
<variation name>v or <variation name>vhd —This variation name
module is created by the MegaWizard interface when files are
generated based on the parameters that you set. For simulation
purposes, the IP functional simulation model produced by the
MegaWizard interface is used. The IP functional simulation model is
either the <variation name>.vho or <variation name>.vo file. The
associated <variation name>.vhd or <variation name>.v file is used by
the Quartus II software during compilation. For information on
producing a functional simulation model, see the Getting Started
chapter.
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PCI Express Compiler Version 6.1
A DMA read and a DMA Write module
On chip EP memory (Avalon slave) which uses two Avalon-MM
buses for each engine
RC Slave module for performance monitoring and single
DWORD Mrd/Mwr
Header Register module: RC programs the descriptor header (4
DWORDS) at the beginning of the DMA
Appendix C,
) which allows you to
Altera Corporation
December 2006