IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 250

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Test-Out Interface Signals for x8 MegaCore Functions
C–20
PCI Express Compiler User Guide
txl0s_sm
timeout
txos_end
tx_ack
tx_ctrl
txrx_det
tx_pad
rx_ts1
rx_ts2
Table C–2. test_out Signals for the x8 MegaCore Functions (Part 2 of 4)
Signal
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
MAC
ltssm
Subblock
PCI Express Compiler Version 6.1
9:7
10
11
12
15:13
23:16
31:24
39:32
47:40
Bit
TX L0s state: Transmit L0s state machine
LTSSM Timeout: This signal serves as a flag that
indicates that the LTSSM timeout condition has been
reached for the current LTSSM state.
Transmit LTSSM exit condition: This signal serves as a
flag that indicates that the LTSSM exit condition for the
next state (in order to go to L0) has been completed. If the
next state is not reached in a timely manner, it is due to a
problem on the receiver.
Transmit PLP acknowledge: This signal is active for 1
clock cycle when the requested PLP (Physical Layer
Packet) has been sent to the Link. The type of packet is
defined by TX_CTRL
Transmit PLP type: This signal
Receiver detect result: This signal serves as a per-lane
flag that reports the receiver detection result.
Force PAD on transmitted TS pattern: This is a per-lane
internal signal that force PAD transmission on the Link and
lane field of the transmitted TS1/TS2 OS. The Core
considers that Lanes indicated by this signal should not be
initialized during the initialization process.
Received TS1: This signal indicates that a TS1 has been
received on the specified Lane. This signal is cleared
when a new state is reached by the LTSSM state machine.
Received TS2: This signal indicates that a TS1 has been
received on the specified Lane. This signal is cleared
when a new state is reached by the LTSSM state machine.
000b: inact
001b: entry
010b: idle
011b: fts
100b: out.l0
000: Electrical Idle
001: Receiver detect during
010: TS1 OS
011: TS2 OS
100: D0.0 idle data
101: FTS OS
110: IDL OS
111: Compliance pattern
.
Description
Altera Corporation
December 2006