IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 232

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Test-Out Interface Signals for x1 and x4 MegaCore Functions
Test-Out
Interface
Signals for
x1 and x4
MegaCore
Functions
C–2
PCI Express Compiler User Guide
rx_fval_tlp
rx_hval_tlp
rx_dval_tlp
rx_check_tlp
rx_discard_tlp
rx_mlf_tlp
tlp_err
rxfc_ovf
rx_ecrcerr_tlp
rx_uns_tlp
rx_sup_tlp
rx_vc_tlp
Table C–1. test_out Signals for the x1 and x4 MegaCore Functions (Part 1 of 17)
Signal
TRN rxtl
TRN rxtl
TRN rxtl
Subblock
Table C–1
functions.
2:0
10:3
13:11
PCI Express Compiler Version 6.1
Bit
describes the test-out signals for the x1 and x4 MegaCore
Receive transaction layer packet reception state. These signals
report the transaction layer packet reception sequencing.
●
●
●
Receive transaction layer packet check state. These signals
report the transaction layer packet reception sequencing:
●
●
●
●
●
●
●
●
If bits 1, 2, 3, or 4 are set, the transaction layer packet is
removed from the receive buffer and no flow control credits are
consumed. If bit 5, 6 or 7 is set, the transaction layer packet is
routed to the configuration space after being written to the
receive buffer and flow control credits are updated.
Receive transaction layer packet virtual channel mapping. This
signal reports the virtual channel resource on which the
transaction layer packet is mapped (according to its traffic
class).
bit 0: DW0 and DW1 of the header are valid
bit 1: DW2 and DW3 of the header are valid
bit 2: The data payload is valid
bit 0: Check LCRC
bit 1: Indicates an LCRC error or sequence number error
bit 2: Indicates a malformed transaction layer packet due to
a mismatch END/length field
bit 3: Indicates a malformed transaction layer packet that
doesn’t conform with formation rules
bit 4: Indicates violation of flow control rules
bit 5: Indicates a ECRC error (flow control credits are
updated)
bit 6: Indicates reception of an unsupported transaction
layer packet (flow control credits are updated)
bit 7: Indicates a transaction layer packet routed to the
Configuration space (flow control credits are updated)
Description
Altera Corporation
December 2006