IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 43

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
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Transmit Virtual Channel Arbitration
The PCI Express MegaCore function allows you to divide the virtual
channels into high and low priority groups as specified in Chapter 6 of
the PCI Express Base Specification 1.1 or the PCI Express Base Specification
Revision 1.0a.
Arbitration of high-priority virtual channels uses a strict priority
arbitration scheme in which higher numbered virtual channels always
have higher priority than lower numbered virtual channels. Low-priority
virtual channels use a fixed round robin arbitration scheme.
You can use the settings on the Buffer Setup page accessible from the
Parameter Settings tab in the MegaWizard interface to specify the
number of virtual channels and the number of virtual channels in the low
priority group. See
Configuration Space
The configuration space implements all configuration registers and
associated functions below.
■
■
■
■
■
The configuration space also generates all messages (PME#, INT, error,
power slot limit, etc.), MSI requests, and completion packets from
configuration requests that flow in the direction of the root complex,
except power slot limit messages, which are generated by a downstream
port in the direction of the PCI Express link. All such transactions are
dependent upon the content of the PCI Express configuration space as
described in the PCI Express™ Base Specification Revision 1.0a.
See
in the PCI Express Base Specification 1.1 or the PCI Express Base Specification
Revision 1.0a for the complete content of these registers.
“Configuration Space Register Content” on page 3–18
Type 0 Configuration Space
PCI Power Management Capability Structure
Message Signaled Interrupt (MSI) Capability Structure
PCI Express Capability Structure
Virtual Channel Capabilities
PCI Express Compiler Version 6.1
“Buffer Setup Page” on page
PCI Express Compiler User Guide
3–37.
or Chapter 7
3–5