IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 119

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Specifications
Altera Corporation
December 2006
pme_to_cr
pme_to_sr
Table 3–32. Power Management Signals (Part 1 of 2)
Signal
I
O
I/O
The x8 MegaCore function has two reset inputs, npor and rstn. The
npor reset is used internally for all sticky registers (registers that may not
be reset in L2 low power mode or by the fundamental reset). npor is
typically generated by a logical OR of the power-on-reset generator and
the perst signal as specified in the PCI Express card electromechanical
specification.
The rstn signal is an asynchronous reset of the data path state machines
and the nonsticky configuration space registers. rstn should be asserted
whenever the l2_exit, hotrst_exit, or dlup_exit signals are
asserted.
The reset block shown in
MegaCore function to provide some flexibility for implementation-
specific methods of generating a reset.
Table 3–32
Power management turn off control register. This signal is asserted to
acknowledge the
root port.
Power management turn off status register. This signal is asserted when the
endpoint receives the
until
pme_to_cr
PCI Express Compiler Version 6.1
shows the function’s power management signals.
PME_turn_off
is asserted.
PME_turn_off
Figure 3–36
Description
message by sending
message from the root port. It is asserted
is not included as part of the
PCI Express Compiler User Guide
pme_to_ack
to the
3–81